1. Technical Field
The present invention relates generally to phase-locked loop circuitry and more particularly to phase-locked loop filter capacitance with a drag current.
2. Description of Related Art
Filter circuitry may contain capacitors to filter certain frequencies of a signal. Filter circuitry is used in numerous types of electronic circuits. One type of electronic circuit is a phase-locked loop. A phase-locked loop (PLL) is an electronic circuit with a voltage- or current-driven oscillator that is adjusted to match in phase (and thus lock on) the frequency of an input signal. In addition, PLLs are used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, and multiply or divide a frequency. Examples of applications for PLLs include frequency synthesizers for RF local oscillators or digital clock generation, recovery of small signals that otherwise would be lost in noise, lock-in amplifiers, and recovery of clock timing information from a data stream.
FIG. 1 illustrates phase-locked loop (PLL) circuitry 100 according to the prior art. Phase-frequency detector (PFD) circuitry 110 generates an “up” signal 115 and a “down” signal 120 by comparing the phase difference of an input signal 105 to a feedback signal 160. The PFD circuitry 110 outputs the up signal 115 and the down signal 120 depending on whether or not the phase of the feedback signal 160 lags (needs to speed up) or leads (needs to slow down) when compared to the input signal 105. Charge pump circuitry 125 generates current pulses in a charge pump output signal 130 (e.g., to charge capacitors in loop filter circuitry 135) based on the up signal 115 and the down signal 120. The current pulses generated by the charge pump circuitry 125 have a finite minimum pulse width in order to avoid a “dead-zone” effect. For example, when the input signal 105 and the feedback signal 160 have equal phase, the current pulses of the charge pump output signal 130 have a non-zero equal width. With unequal phase, one of the current pulses of the charge pump output signal 130 is lengthened to correct the phase.
The loop filter circuitry 135 low pass filters the charge pump output signal 130 and generates a filtered control signal 140. Voltage controlled oscillator (VCO) circuitry 145 generates an output signal 150 whose frequency is determined by the voltage of the filtered control signal 140. The PLL circuitry 100 loops the output signal 150 back to the PFD circuitry 110 as the feedback signal 160. Optionally, frequency divider circuitry 155 is placed in the feedback path of the loop to generate the feedback signal 160 and to allow the frequency of the output signal 150 to be a multiple of the input signal 105.
FIG. 2 illustrates loop filter circuitry 135 according to the prior art. The loop filter circuitry 135 depicted in FIG. 2 is an example of a second order loop filter. The loop filter circuitry 135 includes a capacitor 220, a resistor 230, and a capacitor 240. The charge pump circuitry 125 of FIG. 1 is represented in FIG. 2 as a current source 210. The capacitor 220 is connected to the control voltage node 215 and ground. The resistor 230 is connected to the control voltage node 215 and the capacitor 240. The capacitor 240 is also connected to ground. The control voltage node 215 is also connected to the voltage controlled oscillator circuitry 145 of FIG. 1. Due to stability concerns, the capacitor 240 (i.e. big capacitor) is usually at least ten times larger than the capacitor 220 (i.e. small capacitor). Increasing the size of the capacitor 240 with respect to the capacitor 220 improves phase margin, which is often desirable. However, it is also desirable to make the capacitor 220 (i.e., small capacitor) as large as possible to reduce the ripple on the control voltage. Therefore, in order to achieve good phase margin and ripple suppression, the capacitor 240 may need to be very large.
An important factor in PLL design is the loop bandwidth. The loop bandwidth describes characteristics of the PLL such as settling behavior and noise transfer functions. A very low loop bandwidth is desirable to achieve good filtering of reference clock noise and feedback divider noise. This is especially important in fractional-N PLL applications where the value of the feedback divide is constantly changing and large amounts of quantization noise may be introduced into the loop. Low bandwidth is also a requirement for loop stability when low reference clock frequencies are used. It is typically desirable for the loop bandwidth to be at least 10 times lower than that of the reference clock frequency. For fractional-N PLLs, the reference clock frequency to bandwidth ratios on the order of 100:1 may be used.
A PLL designer typically has two alternatives to achieve a lower loop bandwidth. First, the charge pump current can be decreased. However, decreasing the charge pump current increases its noise contribution and becomes increasingly difficult to implement at low levels.
The other alternative for lowering the loop bandwidth is increasing the size of the loop filter integration capacitor (i.e., big capacitor). Consequently, one limitation is the overall size of the PLL increases because of the increased size of the capacitor. In FIG. 2, the capacitor 220 is 17.5 pF, and the capacitor 240 is 280 pF. In this example, one problem is the big capacitor (i.e., the capacitor 240) at 280 pF occupies a significant area on the integrated circuit in order to achieve a low loop bandwidth. Some low bandwidth PLL designs may use off chip discrete components for the loop filter. However, components are increasingly being implemented on-chip to be fully integrated, which further increases the need to minimize area consumed on the integrated circuit.